System and method for supporting configurable legacy p_key table abstraction using a bitmap based hardware implementation in a high performance computing environment

ABSTRACT

System and method for supporting configurable legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment. A mapping table in DRAM can be provided through the use of a software based SMA that implements the mapping table. With this mapping table, it is possible to provide a legacy compliant view of a bit map based P_Key table. Such a legacy compliant view can be called a virtual P_Key table, or a configurable legacy P_Key table abstraction.

COPYRIGHT NOTICE

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

CLAIM OF PRIORITY AND CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to U.S. Provisional Patent Application entitled “SYSTEM AND METHOD FOR PROVIDING SCALABLE BIT MAP BASED P_KEY TABLE IN A COMPUTING ENVIRONMENT”, Application No. 62/287,704, filed on Jan. 27, 2016, which is incorporated by reference in its entirety.

FIELD OF INVENTION

The present invention is generally related to computer systems, and is particularly related to supporting a configurable legacy P_Key table abstraction in a high performance computing environment.

BACKGROUND

As larger cloud computing architectures are introduced, the performance and administrative bottlenecks associated with the traditional network and storage have become a significant problem. There has been an increased interest in using high performance lossless interconnects such as InfiniBand (IB) technology as the foundation for a cloud computing fabric. This is the general area that embodiments of the invention are intended to address.

SUMMARY

Described herein are systems and methods for supporting legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment. An exemplary method can provide, at one or more computers, including one or more microprocessors, at least one subnet, the at least one subnet comprising one or more switches, the one or more switches comprising at least a leaf switch, wherein each of the one or more switches comprise a plurality of switch ports, a plurality of host channel adapters, each host channel adapter comprising at least one host channel adapter port, and a plurality of end nodes, wherein each of the plurality of end nodes are associated with at least one host channel adapter of the plurality of host channel adapters. The method can associate each of the end nodes with at least one of a plurality of partitions, wherein each of the plurality of partitions are associated with a P_Key value. The method can associate each of the one or more switch ports with a bitmap based P_Key table of a plurality of bitmap based P_Key tables. The method can associate each of the host channel adapter ports with a bitmap based P_Key table of the plurality of bitmap based P_Key tables. The method can associate each of the plurality of bitmap based P_Key tables with a virtual P_Key table.

In accordance with an embodiment, one or more of the plurality of host channel adapters can comprise at least one virtual function, at least one virtual switch, and at least one physical function. The plurality of end nodes can comprise physical hosts, virtual machines, or a combination of physical hosts and virtual machines, wherein the virtual machines are associated with at least one virtual function.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 shows an illustration of an InfiniBand environment, in accordance with an embodiment.

FIG. 2 shows an illustration of a partitioned cluster environment, in accordance with an embodiment

FIG. 3 shows an illustration of a tree topology in a network environment, in accordance with an embodiment.

FIG. 4 shows an exemplary shared port architecture, in accordance with an embodiment.

FIG. 5 shows an exemplary vSwitch architecture, in accordance with an embodiment.

FIG. 6 shows an exemplary vPort architecture, in accordance with an embodiment.

FIG. 7 shows an exemplary vSwitch architecture with prepopulated LIDs, in accordance with an embodiment.

FIG. 8 shows an exemplary vSwitch architecture with dynamic LID assignment, in accordance with an embodiment.

FIG. 9 shows an exemplary vSwitch architecture with vSwitch with dynamic LID assignment and prepopulated LIDs, in accordance with an embodiment.

FIG. 10 shows an exemplary multi-subnet InfiniBand fabric, in accordance with an embodiment.

FIG. 11 shows an exemplary InfiniBand fabric with an associative table for partition isolation, in accordance with an embodiment.

FIG. 12 shows an exemplary InfiniBand fabric with bitmap for partition isolation, in accordance with an embodiment.

FIG. 13 is a flowchart for a method for supporting scalable bitmap based P_Key table in a high performance computing environment, in accordance with an embodiment.

FIG. 14 shows an exemplary fabric with bitmap for partition isolation and a P_Key abstraction for legacy management entity, in accordance with an embodiment.

FIG. 15 shows an exemplary fabric with bitmap for partition isolation and a P_Key abstraction for legacy management entity, in accordance with an embodiment.

FIG. 16 is a flowchart for a method for supporting legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment, in accordance with an embodiment.

DETAILED DESCRIPTION

The invention is illustrated, by way of example and not by way of limitation, in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” or “some” embodiment(s) in this disclosure are not necessarily to the same embodiment, and such references mean at least one. While specific implementations are discussed, it is understood that the specific implementations are provided for illustrative purposes only. A person skilled in the relevant art will recognize that other components and configurations may be used without departing from the scope and spirit of the invention.

Common reference numerals can be used to indicate like elements throughout the drawings and detailed description; therefore, reference numerals used in a figure may or may not be referenced in the detailed description specific to such figure if the element is described elsewhere.

Described herein are systems and methods to support a configurable legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment.

The following description of the invention uses an InfiniBand™ (IB) network as an example for a high performance network. Throughout the following description, reference can be made to the InfiniBand™ specification (also referred to variously as the InfiniBand specification, IB specification, or the legacy IB specification). Such reference is understood to refer to the InfiniBand® Trade Association Architecture Specification, Volume 1, Version 1.3, released March, 2015, available at http://www.inifinibandta.org, which is herein incorporated by reference in its entirety. It will be apparent to those skilled in the art that other types of high performance networks can be used without limitation. The following description also uses the fat-tree topology as an example for a fabric topology. It will be apparent to those skilled in the art that other types of fabric topologies can be used without limitation.

To meet the demands of the cloud in the current era (e.g., Exascale era), it is desirable for virtual machines to be able to utilize low overhead network communication paradigms such as Remote Direct Memory Access (RDMA). RDMA bypasses the OS stack and communicates directly with the hardware, thus, pass-through technology like Single-Root I/O Virtualization (SR-IOV) network adapters can be used. In accordance with an embodiment, a virtual switch (vSwitch) SR-IOV architecture can be provided for applicability in high performance lossless interconnection networks. As network reconfiguration time is critical to make live-migration a practical option, in addition to network architecture, a scalable and topology-agnostic dynamic reconfiguration mechanism can be provided.

In accordance with an embodiment, and furthermore, routing strategies for virtualized environments using vSwitches can be provided, and an efficient routing algorithm for network topologies (e.g., Fat-Tree topologies) can be provided. The dynamic reconfiguration mechanism can be further tuned to minimize imposed overhead in Fat-Trees.

In accordance with an embodiment of the invention, virtualization can be beneficial to efficient resource utilization and elastic resource allocation in cloud computing. Live migration makes it possible to optimize resource usage by moving virtual machines (VMs) between physical servers in an application transparent manner. Thus, virtualization can enable consolidation, on-demand provisioning of resources, and elasticity through live migration.

InfiniBand™

InfiniBand™ (IB) is an open standard lossless network technology developed by the InfiniBand™ Trade Association. The technology is based on a serial point-to-point full-duplex interconnect that offers high throughput and low latency communication, geared particularly towards high-performance computing (HPC) applications and datacenters.

The InfiniBand™ Architecture (IBA) supports a two-layer topological division. At the lower layer, IB networks are referred to as subnets, where a subnet can include a set of hosts interconnected using switches and point-to-point links. At the higher level, an IB fabric constitutes one or more subnets, which can be interconnected using routers.

Within a subnet, hosts can be connected using switches and point-to-point links. Additionally, there can be a master management entity, the subnet manager (SM), which resides on a designated device in the subnet. The subnet manager is responsible for configuring, activating and maintaining the IB subnet. Additionally, the subnet manager (SM) can be responsible for performing routing table calculations in an IB fabric. Here, for example, the routing of the IB network aims at proper load balancing between all source and destination pairs in the local subnet.

Through the subnet management interface, the subnet manager exchanges control packets, which are referred to as subnet management packets (SMPs), with subnet management agents (SMAs). The subnet management agents reside on every IB subnet device. By using SMPs, the subnet manager is able to discover the fabric, configure end nodes and switches, and receive notifications from SMAs.

In accordance with an embodiment, intra-subnet routing in an IB network can be based on linear forwarding tables (LFTs) stored in the switches. The LFTs are calculated by the SM according to the routing mechanism in use. In a subnet, Host Channel Adapter (HCA) ports on the end nodes and switches are addressed using local identifiers (LIDs). Each entry in a linear forwarding table (LFT) consists of a destination LID (DLID) and an output port. Only one entry per LID in the table is supported. When a packet arrives at a switch, its output port is determined by looking up the DLID in the forwarding table of the switch. The routing is deterministic as packets take the same path in the network between a given source-destination pair (LID pair).

Generally, all other subnet managers, excepting the master subnet manager, act in standby mode for fault-tolerance. In a situation where a master subnet manager fails, however, a new master subnet manager is negotiated by the standby subnet managers. The master subnet manager also performs periodic sweeps of the subnet to detect any topology changes and reconfigure the network accordingly.

Furthermore, hosts and switches within a subnet can be addressed using local identifiers (LIDs), and a single subnet can be limited to 49151 unicast LIDs. Besides the LIDs, which are the local addresses that are valid within a subnet, each IB device can have a 64-bit global unique identifier (GUID). A GUID can be used to form a global identifier (GID), which is an IB layer three (L3) address.

The SM can calculate routing tables (i.e., the connections/routes between each pair of nodes within the subnet) at network initialization time. Furthermore, the routing tables can be updated whenever the topology changes, in order to ensure connectivity and optimal performance. During normal operations, the SM can perform periodic light sweeps of the network to check for topology changes. If a change is discovered during a light sweep or if a message (trap) signaling a network change is received by the SM, the SM can reconfigure the network according to the discovered changes.

For example, the SM can reconfigure the network when the network topology changes, such as when a link goes down, when a device is added, or when a link is removed. The reconfiguration steps can include the steps performed during the network initialization. Furthermore, the reconfigurations can have a local scope that is limited to the subnets, in which the network changes occurred. Also, the segmenting of a large fabric with routers may limit the reconfiguration scope.

An example InfiniBand fabric is shown in FIG. 1, which shows an illustration of an InfiniBand environment 100, in accordance with an embodiment. In the example shown in FIG. 1, nodes A-E, 101-105, use the InfiniBand fabric, 120, to communicate, via the respective host channel adapters 111-115. In accordance with an embodiment, the various nodes, e.g., nodes A-E, 101-105, can be represented by various physical devices. In accordance with an embodiment, the various nodes, e.g., nodes A-E, 101-105, can be represented by various virtual devices, such as virtual machines.

Partitioning in InfiniBand

In accordance with an embodiment, IB networks can support partitioning as a security mechanism to provide for isolation of logical groups of systems sharing a network fabric. Each HCA port on a node in the fabric can be a member of one or more partitions. Partition memberships are managed by a centralized partition manager, which can be part of the SM. The SM can configure partition membership information on each port as a table of 16-bit partition keys (P_Keys). The SM can also configure switch and router ports with the partition enforcement tables containing P_Key information associated with the end-nodes that send or receive data traffic through these ports. Additionally, in a general case, partition membership of a switch port can represent a union of all membership indirectly associated with LIDs routed via the port in an egress (towards the link) direction.

In accordance with an embodiment, partitions are logical groups of ports such that the members of a group can only communicate to other members of the same logical group. At host channel adapters (HCAs) and switches, packets can be filtered using the partition membership information to enforce isolation. Packets with invalid partitioning information can be dropped as soon as the packets reaches an incoming port. In partitioned IB systems, partitions can be used to create tenant clusters. With partition enforcement in place, a node cannot communicate with other nodes that belong to a different tenant cluster. In this way, the security of the system can be guaranteed even in the presence of compromised or malicious tenant nodes.

In accordance with an embodiment, for the communication between nodes, Queue Pairs (QPs) and End-to-End contexts (EECs) can be assigned to a particular partition, except for the management Queue Pairs (QP0 and QP1). The P_Key information can then be added to every IB transport packet sent. When a packet arrives at an HCA port or a switch, its P_Key value can be validated against a table configured by the SM. If an invalid P_Key value is found, the packet is discarded immediately. In this way, communication is allowed only between ports sharing a partition.

An example of IB partitions is shown in FIG. 2, which shows an illustration of a partitioned cluster environment, in accordance with an embodiment. In the example shown in FIG. 2, nodes A-E, 101-105, use the InfiniBand fabric, 120, to communicate, via the respective host channel adapters 111-115. The nodes A-E are arranged into partitions, namely partition 1, 130, partition 2, 140, and partition 3, 150. Partition 1 comprises node A 101 and node D 104. Partition 2 comprises node A 101, node B 102, and node C 103. Partition 3 comprises node C 103 and node E 105. Because of the arrangement of the partitions, node D 104 and node E 105 are not allowed to communicate as these nodes do not share a partition. Meanwhile, for example, node A 101 and node C 103 are allowed to communicate as these nodes are both members of partition 2, 140.

Virtual Machines in InfiniBand

During the last decade, the prospect of virtualized High Performance Computing (HPC) environments has improved considerably as CPU overhead has been practically removed through hardware virtualization support; memory overhead has been significantly reduced by virtualizing the Memory Management Unit; storage overhead has been reduced by the use of fast SAN storages or distributed networked file systems; and network I/O overhead has been reduced by the use of device passthrough techniques like Single Root Input/Output Virtualization (SR-IOV). It is now possible for clouds to accommodate virtual HPC (vHPC) clusters using high performance interconnect solutions and deliver the necessary performance.

However, when coupled with lossless networks, such as InfiniBand (IB), certain cloud functionality, such as live migration of virtual machines (VMs), still remains an issue due to the complicated addressing and routing schemes used in these solutions. IB is an interconnection network technology offering high bandwidth and low latency, thus, is very well suited for HPC and other communication intensive workloads.

The traditional approach for connecting IB devices to VMs is by utilizing SR-IOV with direct assignment. However, achieving live migration of VMs assigned with IB Host Channel Adapters (HCAs) using SR-IOV has proved to be challenging. Each IB connected node has three different addresses: LID, GUID, and GID. When a live migration happens, one or more of these addresses change. Other nodes communicating with the VM-in-migration can lose connectivity. When this happens, the lost connection can be attempted to be renewed by locating the virtual machine's new address to reconnect to by sending Subnet Administration (SA) path record queries to the IB Subnet Manager (SM).

IB uses three different types of addresses. A first type of address is the 16 bits Local Identifier (LID). At least one unique LID is assigned to each HCA port and each switch by the SM. The LIDs are used to route traffic within a subnet. Since the LID is 16 bits long, 65536 unique address combinations can be made, of which only 49151 (0x0001-0xBFFF) can be used as unicast addresses. Consequently, the number of available unicast addresses defines the maximum size of an IB subnet. A second type of address is the 64 bits Global Unique Identifier (GUID) assigned by the manufacturer to each device (e.g. HCAs and switches) and each HCA port. The SM may assign additional subnet unique GUIDs to an HCA port, which is useful when SR-IOV is used. A third type of address is the 128 bits Global Identifier (GID). The GID is a valid IPv6 unicast address, and at least one is assigned to each HCA port. The GID is formed by combining a globally unique 64 bits prefix assigned by the fabric administrator, and the GUID address of each HCA port.

Fat-Tree (FTree) Topologies and Routing

In accordance with an embodiment, some of the IB based HPC systems employ a fat-tree topology to take advantage of the useful properties fat-trees offer. These properties include full bisection-bandwidth and inherent fault-tolerance due to the availability of multiple paths between each source destination pair. The initial idea behind fat-trees was to employ fatter links between nodes, with more available bandwidth, as the tree moves towards the roots of the topology. The fatter links can help to avoid congestion in the upper-level switches and the bisection-bandwidth is maintained.

FIG. 3 shows an illustration of a tree topology in a network environment, in accordance with an embodiment. As shown in FIG. 3, one or more end nodes 201-204 can be connected in a network fabric 200. The network fabric 200 can be based on a fat-tree topology, which includes a plurality of leaf switches 211-214, and multiple spine switches or root switches 231-234. Additionally, the network fabric 200 can include one or more intermediate switches, such as switches 221-224.

Also as shown in FIG. 3, each of the end nodes 201-204 can be a multi-homed node, i.e., a single node that is connected to two or more parts of the network fabric 200 through multiple ports. For example, the node 201 can include the ports H1 and H2, the node 202 can include the ports H3 and H4, the node 203 can include the ports H5 and H6, and the node 204 can include the ports H7 and H8.

Additionally, each switch can have multiple switch ports. For example, the root switch 231 can have the switch ports 1-2, the root switch 232 can have the switch ports 3-4, the root switch 233 can have the switch ports 5-6, and the root switch 234 can have the switch ports 7-8.

In accordance with an embodiment, the fat-tree routing mechanism is one of the most popular routing algorithm for IB based fat-tree topologies. The fat-tree routing mechanism is also implemented in the OFED (Open Fabric Enterprise Distribution—a standard software stack for building and deploying IB based applications) subnet manager, OpenSM.

The fat-tree routing mechanism aims to generate LFTs that evenly spread shortest-path routes across the links in the network fabric. The mechanism traverses the fabric in the indexing order and assigns target LIDs of the end nodes, and thus the corresponding routes, to each switch port. For the end nodes connected to the same leaf switch, the indexing order can depend on the switch port to which the end node is connected (i.e., port numbering sequence). For each port, the mechanism can maintain a port usage counter, and can use this port usage counter to select a least-used port each time a new route is added.

In accordance with an embodiment, in a partitioned subnet, nodes that are not members of a common partition are not allowed to communicate. Practically, this means that some of the routes assigned by the fat-tree routing algorithm are not used for the user traffic. The problem arises when the fat tree routing mechanism generates LFTs for those routes the same way it does for the other functional paths. This behavior can result in degraded balancing on the links, as nodes are routed in the order of indexing. As routing can be performed oblivious to the partitions, fat-tree routed subnets, in general, provide poor isolation among partitions.

In accordance with an embodiment, a Fat-Tree is a hierarchical network topology that can scale with the available network resources. Moreover, Fat-Trees are easy to build using commodity switches placed on different levels of the hierarchy. Different variations of Fat-Trees are commonly available, including k-ary-n-trees, Extended Generalized Fat-Trees (XGFTs), Parallel Ports Generalized Fat-Trees (PGFTs) and Real Life Fat-Trees (RLFTs).

A k-ary-n-tree is an n level Fat-Tree with k^(n) end nodes and n·k^(n−1) switches, each with 2 k ports. Each switch has an equal number of up and down connections in the tree. XGFT Fat-Tree extends k-ary-n-trees by allowing both different number of up and down connections for the switches, and different number of connections at each level in the tree. The PGFT definition further broadens the XGFT topologies and permits multiple connections between switches. A large variety of topologies can be defined using XGFTs and PGFTs. However, for practical purposes, RLFT, which is a restricted version of PGFT, is introduced to define Fat-Trees commonly found in today's HPC clusters. An RLFT uses the same port-count switches at all levels in the Fat-Tree.

Input/Output (I/O) Virtualization

In accordance with an embodiment, I/O Virtualization (IOV) can provide availability of I/O by allowing virtual machines (VMs) to access the underlying physical resources. The combination of storage traffic and inter-server communication impose an increased load that may overwhelm the I/O resources of a single server, leading to backlogs and idle processors as they are waiting for data. With the increase in number of I/O requests, IOV can provide availability; and can improve performance, scalability and flexibility of the (virtualized) I/O resources to match the level of performance seen in modern CPU virtualization.

In accordance with an embodiment, IOV is desired as it can allow sharing of I/O resources and provide protected access to the resources from the VMs. IOV decouples a logical device, which is exposed to a VM, from its physical implementation. Currently, there can be different types of IOV technologies, such as emulation, paravirtualization, direct assignment (DA), and single root-I/O virtualization (SR-IOV).

In accordance with an embodiment, one type of IOV technology is software emulation. Software emulation can allow for a decoupled front-end/back-end software architecture. The front-end can be a device driver placed in the VM, communicating with the back-end implemented by a hypervisor to provide I/O access. The physical device sharing ratio is high and live migrations of VMs are possible with just a few milliseconds of network downtime. However, software emulation introduces additional, undesired computational overhead.

In accordance with an embodiment, another type of IOV technology is direct device assignment. Direct device assignment involves a coupling of I/O devices to VMs, with no device sharing between VMs. Direct assignment, or device passthrough, provides near to native performance with minimum overhead. The physical device bypasses the hypervisor and is directly attached to the VM. However, a downside of such direct device assignment is limited scalability, as there is no sharing among virtual machines—one physical network card is coupled with one VM.

In accordance with an embodiment, Single Root IOV (SR-IOV) can allow a physical device to appear through hardware virtualization as multiple independent lightweight instances of the same device. These instances can be assigned to VMs as passthrough devices, and accessed as Virtual Functions (VFs). The hypervisor accesses the device through a unique (per device), fully featured Physical Function (PF). SR-IOV eases the scalability issue of pure direct assignment. However, a problem presented by SR-IOV is that it can impair VM migration. Among these IOV technologies, SR-IOV can extend the PCI Express (PCIe) specification with the means to allow direct access to a single physical device from multiple VMs while maintaining near to native performance. Thus, SR-IOV can provide good performance and scalability.

SR-IOV allows a PCIe device to expose multiple virtual devices that can be shared between multiple guests by allocating one virtual device to each guest. Each SR-IOV device has at least one physical function (PF) and one or more associated virtual functions (VF). A PF is a normal PCIe function controlled by the virtual machine monitor (VMM), or hypervisor, whereas a VF is a light-weight PCIe function. Each VF has its own base address (BAR) and is assigned with a unique requester ID that enables I/O memory management unit (IOMMU) to differentiate between the traffic streams to/from different VFs. The IOMMU also apply memory and interrupt translations between the PF and the VFs.

Unfortunately, however, direct device assignment techniques pose a barrier for cloud providers in situations where transparent live migration of virtual machines is desired for data center optimization. The essence of live migration is that the memory contents of a VM are copied to a remote hypervisor. Then the VM is paused at the source hypervisor, and the VM's operation is resumed at the destination. When using software emulation methods, the network interfaces are virtual so their internal states are stored into the memory and get copied as well. Thus the downtime could be brought down to a few milliseconds.

However, migration becomes more difficult when direct device assignment techniques, such as SR-IOV, are used. In such situations, a complete internal state of the network interface cannot be copied as it is tied to the hardware. The SR-IOV VFs assigned to a VM are instead detached, the live migration will run, and a new VF will be attached at the destination. In the case of InfiniBand and SR-IOV, this process can introduce downtime in the order of seconds. Moreover, in an SR-IOV shared port model the addresses of the VM will change after the migration, causing additional overhead in the SM and a negative impact on the performance of the underlying network fabric.

InfiniBand SR-IOV Architecture—Shared Port

There can be different types of SR-IOV models, e.g. a shared port model, a virtual switch model, and a virtual port model.

FIG. 4 shows an exemplary shared port architecture, in accordance with an embodiment. As depicted in the figure, a host 300 (e.g., a host channel adapter) can interact with a hypervisor 310, which can assign the various virtual functions 330, 340, 350, to a number of virtual machines. As well, the physical function can be handled by the hypervisor 310.

In accordance with an embodiment, when using a shared port architecture, such as that depicted in FIG. 4, the host, e.g., HCA, appears as a single port in the network with a single shared LID and shared Queue Pair (QP) space between the physical function 320 and the virtual functions 330, 350, 350. However, each function (i.e., physical function and virtual functions) can have their own GID.

As shown in FIG. 4, in accordance with an embodiment, different GIDs can be assigned to the virtual functions and the physical function, and the special queue pairs, QP0 and QP1 (i.e., special purpose queue pairs that are used for InfiniBand management packets), are owned by the physical function. These QPs are exposed to the VFs as well, but the VFs are not allowed to use QP0 (all SMPs coming from VFs towards QP0 are discarded), and QP1 can act as a proxy of the actual QP1 owned by the PF.

In accordance with an embodiment, the shared port architecture can allow for highly scalable data centers that are not limited by the number of VMs (which attach to the network by being assigned to the virtual functions), as the LID space is only consumed by physical machines and switches in the network.

However, a shortcoming of the shared port architecture is the inability to provide transparent live migration, hindering the potential for flexible VM placement. As each LID is associated with a specific hypervisor, and shared among all VMs residing on the hypervisor, a migrating VM (i.e., a virtual machine migrating to a destination hypervisor) has to have its LID changed to the LID of the destination hypervisor. Furthermore, as a consequence of the restricted QP0 access, a subnet manager cannot run inside a VM.

InfiniBand SR-IOV Architecture Models—Virtual Switch (vSwitch)

FIG. 5 shows an exemplary vSwitch architecture, in accordance with an embodiment. As depicted in the figure, a host 400 (e.g., a host channel adapter) can interact with a hypervisor 410, which can assign the various virtual functions 430, 440, 450, to a number of virtual machines. As well, the physical function can be handled by the hypervisor 410. A virtual switch 415 can also be handled by the hypervisor 401.

In accordance with an embodiment, in a vSwitch architecture each virtual function 430, 440, 450 is a complete virtual Host Channel Adapter (vHCA), meaning that the VM assigned to a VF is assigned a complete set of IB addresses (e.g., GID, GUID, LID) and a dedicated QP space in the hardware. For the rest of the network and the SM, the HCA 400 looks like a switch, via the virtual switch 415, with additional nodes connected to it. The hypervisor 410 can use the PF 420, and the VMs (attached to the virtual functions) use the VFs.

In accordance with an embodiment, a vSwitch architecture provide transparent virtualization. However, because each virtual function is assigned a unique LID, the number of available LIDs gets consumed rapidly. As well, with many LID addresses in use (i.e., one each for each physical function and each virtual function), more communication paths have to be computed by the SM and more Subnet Management Packets (SMPs) have to be sent to the switches in order to update their LFTs. For example, the computation of the communication paths might take several minutes in large networks. Because LID space is limited to 49151 unicast LIDs, and as each VM (via a VF), physical node, and switch occupies one LID each, the number of physical nodes and switches in the network limits the number of active VMs, and vice versa.

InfiniBand SR-IOV Architecture Models—Virtual Port (vPort)

FIG. 6 shows an exemplary vPort concept, in accordance with an embodiment. As depicted in the figure, a host 300 (e.g., a host channel adapter) can interact with a hypervisor 410, which can assign the various virtual functions 330, 340, 350, to a number of virtual machines. As well, the physical function can be handled by the hypervisor 310.

In accordance with an embodiment, the vPort concept is loosely defined in order to give freedom of implementation to vendors (e.g. the definition does not rule that the implementation has to be SRIOV specific), and a goal of the vPort is to standardize the way VMs are handled in subnets. With the vPort concept, both SR-IOV Shared-Port-like and vSwitch-like architectures or a combination of both, that can be more scalable in both the space and performance domains, can be defined. A vPort supports optional LIDs, and unlike the Shared-Port, the SM is aware of all the vPorts available in a subnet even if a vPort is not using a dedicated LID.

InfiniBand SR-IOV Architecture Models—vSwitch with Prepopulated LIDs

In accordance with an embodiment, the present disclosure provides a system and method for providing a vSwitch architecture with prepopulated LIDs.

FIG. 7 shows an exemplary vSwitch architecture with prepopulated LIDs, in accordance with an embodiment. As depicted in the figure, a number of switches 501-504 can provide communication within the network switched environment 600 (e.g., an IB subnet) between members of a fabric, such as an InfiniBand fabric. The fabric can include a number of hardware devices, such as host channel adapters 510, 520, 530. Each of the host channel adapters 510, 520, 530, can in turn interact with a hypervisor 511, 521, and 531, respectively. Each hypervisor can, in turn, in conjunction with the host channel adapter it interacts with, setup and assign a number of virtual functions 514, 515, 516, 524, 525, 526, 534, 535, 536, to a number of virtual machines. For example, virtual machine 1 550 can be assigned by the hypervisor 511 to virtual function 1 514. Hypervisor 511 can additionally assign virtual machine 2 551 to virtual function 2 515, and virtual machine 3 552 to virtual function 3 516. Hypervisor 531 can, in turn, assign virtual machine 4 553 to virtual function 1 534. The hypervisors can access the host channel adapters through a fully featured physical function 513, 523, 533, on each of the host channel adapters.

In accordance with an embodiment, each of the switches 501-504 can comprise a number of ports (not shown), which are used in setting a linear forwarding table in order to direct traffic within the network switched environment 600.

In accordance with an embodiment, the virtual switches 512, 522, and 532, can be handled by their respective hypervisors 511, 521, 531. In such a vSwitch architecture each virtual function is a complete virtual Host Channel Adapter (vHCA), meaning that the VM assigned to a VF is assigned a complete set of IB addresses (e.g., GID, GUID, LID) and a dedicated QP space in the hardware. For the rest of the network and the SM (not shown), the HCAs 510, 520, and 530 look like a switch, via the virtual switches, with additional nodes connected to them.

In accordance with an embodiment, the present disclosure provides a system and method for providing a vSwitch architecture with prepopulated LIDs. Referring to FIG. 7, the LIDs are prepopulated to the various physical functions 513, 523, 533, as well as the virtual functions 514-516, 524-526, 534-536 (even those virtual functions not currently associated with an active virtual machine). For example, physical function 513 is prepopulated with LID 1, while virtual function 1 534 is prepopulated with LID 10. The LIDs are prepopulated in an SR-IOV vSwitch-enabled subnet when the network is booted. Even when not all of the VFs are occupied by VMs in the network, the populated VFs are assigned with a LID as shown in FIG. 7.

In accordance with an embodiment, much like physical host channel adapters can have more than one port (two ports are common for redundancy), virtual HCAs can also be represented with two ports and be connected via one, two or more virtual switches to the external IB subnet.

In accordance with an embodiment, in a vSwitch architecture with prepopulated LIDs, each hypervisor can consume one LID for itself through the PF and one more LID for each additional VF. The sum of all the VFs available in all hypervisors in an IB subnet, gives the maximum amount of VMs that are allowed to run in the subnet. For example, in an IB subnet with 16 virtual functions per hypervisor in the subnet, then each hypervisor consumes 17 LIDs (one LID for each of the 16 virtual functions plus one LID for the physical function) in the subnet. In such an IB subnet, the theoretical hypervisor limit for a single subnet is ruled by the number of available unicast LIDs and is: 2891 (49151 available LIDs divided by 17 LIDs per hypervisor), and the total number of VMs (i.e., the limit) is 46256 (2891 hypervisors times 16 VFs per hypervisor). (In actuality, these numbers are actually smaller since each switch, router, or dedicated SM node in the IB subnet consumes a LID as well). Note that the vSwitch does not need to occupy an additional LID as it can share the LID with the PF

In accordance with an embodiment, in a vSwitch architecture with prepopulated LIDs, communication paths are computed for all the LIDs the first time the network is booted. When a new VM needs to be started the system does not have to add a new LID in the subnet, an action that would otherwise cause a complete reconfiguration of the network, including path recalculation, which is the most time consuming part. Instead, an available port for a VM is located (i.e., an available virtual function) in one of the hypervisors and the virtual machine is attached to the available virtual function.

In accordance with an embodiment, a vSwitch architecture with prepopulated LIDs also allows for the ability to calculate and use different paths to reach different VMs hosted by the same hypervisor. Essentially, this allows for such subnets and networks to use a LID Mask Control (LMC) like feature to provide alternative paths towards one physical machine, without being bound by the limitation of the LMC that requires the LIDs to be sequential. The freedom to use non-sequential LIDs is particularly useful when a VM needs to be migrated and carry its associated LID to the destination.

In accordance with an embodiment, along with the benefits shown above of a vSwitch architecture with prepopulated LIDs, certain considerations can be taken into account. For example, because the LIDs are prepopulated in an SR-IOV vSwitch-enabled subnet when the network is booted, the initial path computation (e.g., on boot-up) can take longer than if the LIDs were not prepopulated.

InfiniBand SR-IOV Architecture Models—vSwitch with Dynamic LID Assignment

In accordance with an embodiment, the present disclosure provides a system and method for providing a vSwitch architecture with dynamic LID assignment.

FIG. 8 shows an exemplary vSwitch architecture with dynamic LID assignment, in accordance with an embodiment. As depicted in the figure, a number of switches 501-504 can provide communication within the network switched environment 700 (e.g., an IB subnet) between members of a fabric, such as an InfiniBand fabric. The fabric can include a number of hardware devices, such as host channel adapters 510, 520, 530. Each of the host channel adapters 510, 520, 530, can in turn interact with a hypervisor 511, 521, 531, respectively. Each hypervisor can, in turn, in conjunction with the host channel adapter it interacts with, setup and assign a number of virtual functions 514, 515, 516, 524, 525, 526, 534, 535, 536, to a number of virtual machines. For example, virtual machine 1 550 can be assigned by the hypervisor 511 to virtual function 1 514. Hypervisor 511 can additionally assign virtual machine 2 551 to virtual function 2 515, and virtual machine 3 552 to virtual function 3 516. Hypervisor 531 can, in turn, assign virtual machine 4 553 to virtual function 1 534. The hypervisors can access the host channel adapters through a fully featured physical function 513, 523, 533, on each of the host channel adapters.

In accordance with an embodiment, each of the switches 501-504 can comprise a number of ports (not shown), which are used in setting a linear forwarding table in order to direct traffic within the network switched environment 700.

In accordance with an embodiment, the virtual switches 512, 522, and 532, can be handled by their respective hypervisors 511, 521, 531. In such a vSwitch architecture each virtual function is a complete virtual Host Channel Adapter (vHCA), meaning that the VM assigned to a VF is assigned a complete set of IB addresses (e.g., GID, GUID, LID) and a dedicated QP space in the hardware. For the rest of the network and the SM (not shown), the HCAs 510, 520, and 530 look like a switch, via the virtual switches, with additional nodes connected to them.

In accordance with an embodiment, the present disclosure provides a system and method for providing a vSwitch architecture with dynamic LID assignment. Referring to FIG. 8, the LIDs are dynamically assigned to the various physical functions 513, 523, 533, with physical function 513 receiving LID 1, physical function 523 receiving LID 2, and physical function 533 receiving LID 3. Those virtual functions that are associated with an active virtual machine can also receive a dynamically assigned LID. For example, because virtual machine 1 550 is active and associated with virtual function 1 514, virtual function 514 can be assigned LID 5. Likewise, virtual function 2 515, virtual function 3 516, and virtual function 1 534 are each associated with an active virtual function. Because of this, these virtual functions are assigned LIDs, with LID 7 being assigned to virtual function 2 515, LID 11 being assigned to virtual function 3 516, and LID 9 being assigned to virtual function 1 534. Unlike vSwitch with prepopulated LIDs, those virtual functions not currently associated with an active virtual machine do not receive a LID assignment.

In accordance with an embodiment, with the dynamic LID assignment, the initial path computation can be substantially reduced. When the network is booting for the first time and no VMs are present then a relatively small number of LIDs can be used for the initial path calculation and LFT distribution.

In accordance with an embodiment, much like physical host channel adapters can have more than one port (two ports are common for redundancy), virtual HCAs can also be represented with two ports and be connected via one, two or more virtual switches to the external IB subnet.

In accordance with an embodiment, when a new VM is created in a system utilizing vSwitch with dynamic LID assignment, a free VM slot is found in order to decide on which hypervisor to boot the newly added VM, and a unique non-used unicast LID is found as well. However, there are no known paths in the network and the LFTs of the switches for handling the newly added LID. Computing a new set of paths in order to handle the newly added VM is not desirable in a dynamic environment where several VMs may be booted every minute. In large IB subnets, computing a new set of routes can take several minutes, and this procedure would have to repeat each time a new VM is booted.

Advantageously, in accordance with an embodiment, because all the VFs in a hypervisor share the same uplink with the PF, there is no need to compute a new set of routes. It is only needed to iterate through the LFTs of all the physical switches in the network, copy the forwarding port from the LID entry that belongs to the PF of the hypervisor—where the VM is created—to the newly added LID, and send a single SMP to update the corresponding LFT block of the particular switch. Thus the system and method avoids the need to compute a new set of routes.

In accordance with an embodiment, the LIDs assigned in the vSwitch with dynamic LID assignment architecture do not have to be sequential. When comparing the LIDs assigned on VMs on each hypervisor in vSwitch with prepopulated LIDs versus vSwitch with dynamic LID assignment, it is notable that the LIDs assigned in the dynamic LID assignment architecture are non-sequential, while those prepopulated in are sequential in nature. In the vSwitch dynamic LID assignment architecture, when a new VM is created, the next available LID is used throughout the lifetime of the VM. Conversely, in a vSwitch with prepopulated LIDs, each VM inherits the LID that is already assigned to the corresponding VF, and in a network without live migrations, VMs consecutively attached to a given VF get the same LID.

In accordance with an embodiment, the vSwitch with dynamic LID assignment architecture can resolve the drawbacks of the vSwitch with prepopulated LIDs architecture model at a cost of some additional network and runtime SM overhead. Each time a VM is created, the LFTs of the physical switches in the subnet are updated with the newly added LID associated with the created VM. One subnet management packet (SMP) per switch is needed to be sent for this operation. The LMC-like functionality is also not available, because each VM is using the same path as its host hypervisor. However, there is no limitation on the total amount of VFs present in all hypervisors, and the number of VFs may exceed that of the unicast LID limit. Of course, not all of the VFs are allowed to be attached on active VMs simultaneously if this is the case, but having more spare hypervisors and VFs adds flexibility for disaster recovery and optimization of fragmented networks when operating close to the unicast LID limit.

InfiniBand SR-IOV Architecture Models—vSwitch with Dynamic LID Assignment and Prepopulated LIDs

FIG. 9 shows an exemplary vSwitch architecture with vSwitch with dynamic LID assignment and prepopulated LIDs, in accordance with an embodiment. As depicted in the figure, a number of switches 501-504 can provide communication within the network switched environment 800 (e.g., an IB subnet) between members of a fabric, such as an InfiniBand fabric. The fabric can include a number of hardware devices, such as host channel adapters 510, 520, 530. Each of the host channel adapters 510, 520, 530, can in turn interact with a hypervisor 511, 521, and 531, respectively. Each hypervisor can, in turn, in conjunction with the host channel adapter it interacts with, setup and assign a number of virtual functions 514, 515, 516, 524, 525, 526, 534, 535, 536, to a number of virtual machines. For example, virtual machine 1 550 can be assigned by the hypervisor 511 to virtual function 1 514. Hypervisor 511 can additionally assign virtual machine 2 551 to virtual function 2 515. Hypervisor 521 can assign virtual machine 3 552 to virtual function 3 526. Hypervisor 531 can, in turn, assign virtual machine 4 553 to virtual function 2 535. The hypervisors can access the host channel adapters through a fully featured physical function 513, 523, 533, on each of the host channel adapters.

In accordance with an embodiment, each of the switches 501-504 can comprise a number of ports (not shown), which are used in setting a linear forwarding table in order to direct traffic within the network switched environment 800.

In accordance with an embodiment, the virtual switches 512, 522, and 532, can be handled by their respective hypervisors 511, 521, 531. In such a vSwitch architecture each virtual function is a complete virtual Host Channel Adapter (vHCA), meaning that the VM assigned to a VF is assigned a complete set of IB addresses (e.g., GID, GUID, LID) and a dedicated QP space in the hardware. For the rest of the network and the SM (not shown), the HCAs 510, 520, and 530 look like a switch, via the virtual switches, with additional nodes connected to them.

In accordance with an embodiment, the present disclosure provides a system and method for providing a hybrid vSwitch architecture with dynamic LID assignment and prepopulated LIDs. Referring to FIG. 9, hypervisor 511 can be arranged with vSwitch with prepopulated LIDs architecture, while hypervisor 521 can be arranged with vSwitch with prepopulated LIDs and dynamic LID assignment. Hypervisor 531 can be arranged with vSwitch with dynamic LID assignment. Thus, the physical function 513 and virtual functions 514-516 have their LIDs prepopulated (i.e., even those virtual functions not attached to an active virtual machine are assigned a LID). Physical function 523 and virtual function 1 524 can have their LIDs prepopulated, while virtual function 2 and 3, 525 and 526, have their LIDs dynamically assigned (i.e., virtual function 2 525 is available for dynamic LID assignment, and virtual function 3 526 has a LID of 11 dynamically assigned as virtual machine 3 552 is attached). Finally, the functions (physical function and virtual functions) associated with hypervisor 3 531 can have their LIDs dynamically assigned. This results in virtual functions 1 and 3, 534 and 536, are available for dynamic LID assignment, while virtual function 2 535 has LID of 9 dynamically assigned as virtual machine 4 553 is attached there.

In accordance with an embodiment, such as that depicted in FIG. 9, where both vSwitch with prepopulated LIDs and vSwitch with dynamic LID assignment are utilized (independently or in combination within any given hypervisor), the number of prepopulated LIDs per host channel adapter can be defined by a fabric administrator and can be in the range of 0<=prepopulated VFs<=Total VFs (per host channel adapter), and the VFs available for dynamic LID assignment can be found by subtracting the number of prepopulated VFs from the total number of VFs (per host channel adapter).

In accordance with an embodiment, much like physical host channel adapters can have more than one port (two ports are common for redundancy), virtual HCAs can also be represented with two ports and be connected via one, two or more virtual switches to the external IB subnet.

InfiniBand—Inter-Subnet Communication (Fabric Manager)

In accordance with an embodiment, in addition to providing an InfiniBand fabric within a single subnet, embodiments of the current disclosure can also provide for an InfiniBand fabric that spans two or more subnets.

FIG. 10 shows an exemplary multi-subnet InfiniBand fabric, in accordance with an embodiment. As depicted in the figure, within subnet A 1000, a number of switches 1001-1004 can provide communication within subnet A 1000 (e.g., an IB subnet) between members of a fabric, such as an InfiniBand fabric. The fabric can include a number of hardware devices, such as, for example, channel adapter 1010. Host channel adapters 1010 can in turn interact with a hypervisor 1011. The hypervisor can, in turn, in conjunction with the host channel adapter it interacts with, setup a number of virtual functions 1014. The hypervisor can additionally assign virtual machines to each of the virtual functions, such as virtual machine 1 10105 being assigned to virtual function 1 1014. The hypervisor can access their associated host channel adapters through a fully featured physical function, such as physical function 1013, on each of the host channel adapters. Within subnet B 1040, a number of switches 1021-1024 can provide communication within subnet b 1040 (e.g., an IB subnet) between members of a fabric, such as an InfiniBand fabric. The fabric can include a number of hardware devices, such as, for example, channel adapter 1030. Host channel adapters 1030 can in turn interact with a hypervisor 1031. The hypervisor can, in turn, in conjunction with the host channel adapter it interacts with, setup a number of virtual functions 1034. The hypervisor can additionally assign virtual machines to each of the virtual functions, such as virtual machine 2 1035 being assigned to virtual function 2 1034. The hypervisor can access their associated host channel adapters through a fully featured physical function, such as physical function 1033, on each of the host channel adapters. It is noted that although only one host channel adapter is shown within each subnet (i.e., subnet A and subnet B), it is to be understood that a plurality of host channel adapters, and their corresponding components, can be included within each subnet.

In accordance with an embodiment, each of the host channel adapters can additionally be associated with a virtual switch, such as virtual switch 1012 and virtual switch 1032, and each HCA can be set up with a different architecture model, as discussed above. Although both subnets within FIG. 10 are shown as using a vSwitch with prepopulated LID architecture model, this is not meant to imply that all such subnet configurations must follow a similar architecture model.

In accordance with an embodiment, at least one switch within each subnet can be associated with a router, such as switch 1002 within subnet A 1000 being associated with router 1005, and switch 1021 within subnet B 1040 being associated with router 1006.

In accordance with an embodiment, at least one device (e.g., a switch, a node . . . etc.) can be associated with a fabric manager (not shown). The fabric manager can be used, for example, to discover inter-subnet fabric topology, created a fabric profile (e.g., a virtual machine fabric profile), build a virtual machine related database objects that forms the basis for building a virtual machine fabric profile. In addition, the fabric manager can define legal inter-subnet connectivity in terms of which subnets are allowed to communicate via which router ports using which partition numbers.

In accordance with an embodiment, when traffic at an originating source, such as virtual machine 1 within subnet A, is addressed to a destination at a different subnet, such as virtual machine 2 within subnet B, the traffic can be addressed to the router within subnet A, i.e., router 1005, which can then pass the traffic to subnet B via its link with router 1006.

Scalable Bitmap Based P_Key Table

In accordance with an embodiment, because of the expanded InfiniBand networks provided with the use of virtual machines, the number of possible partitions within has increased dramatically. However, with the current method for handling P_Key administration and routing, significant overhead time is added as traffic traverses the fabric. Traditionally, the InfiniBand specification defines a P_Key table as an array of 16 bit P_Key values that the SM can access as an indexed table. A hardware implementation of this specification implies the use of associative memory to perform lookup to perform partition checking of IB packets at wire-speed packet rate. Practically, this limits the possible size of a hardware implemented P_Key table to be orders of magnitude smaller that the 64K value space that the 16 bit P_Key value represents.

In accordance with an embodiment, the InfiniBand specification defines partition membership via a 16 bit P_Key, and enforces partition isolation through the use of a fixed table of P_Key values at each port within the fabric. The Subnet Manager can program different P_Key values in different table entries. When a packet, marked in its header with a P_Key based upon its partition association, arrives at a port, the underlying hardware can compare the incoming packet with all the values in the P_Key table associated with the checking hardware (i.e., performing an associative lookup at the table). However, this lookup does not scale well with a large number of partitions and can introduce unwanted overhead while performing lookups on a number of partitions within the table.

FIG. 11 shows an exemplary InfiniBand fabric with an associative table for partition isolation, in accordance with an embodiment. As shown in FIG. 11, one or more end nodes 1141-1144 can be connected in a network fabric 1100. The network fabric 1100 can be based on a fat-tree topology, which includes a plurality of leaf switches 1111-1114, and multiple spine switches or root switches 1131-1134. Additionally, the network fabric 1100 can include one or more intermediate switches, such as switches 1121-1124. Also as shown in FIG. 11, each of the end nodes 1141-1144 can be a multi-homed node.

In accordance with an embodiment, each of the nodes 1141-1144 can belong to one or more of a number of partitions, where each partition is associated with a P_Key value. As described above, the P_Key value can be included in each packet sent within the fabric, and can allow for varying degrees of partition enforcement within the subnet. Each of the P_Key values are stored in a number of tables, for example tables 1101-1108 (also referred to herein as “port P_Key table”), where each table is associated with, for example, a port of a switch or another member of the fabric, such as a HCA port belonging to a host node. Each table 1101-1108 can be set by the subnet manager.

In accordance with an embodiment, each port P_Key table can comprise an array of N entries where each entry can contain a 16 bit P_Key value, and the value of N is a capability of the port (retrieved by the SM as part of discovering the status and capabilities of the port). When the SM has policy information that implies that a port should be member of a partition (i.e., full or limited), the SM can find the next available entry in the port P_Key table and then store the relevant 16 bit P_Key value in that entry. Once a P_Key value has been successfully stored (confirmed by the SMA to the SM), the SM can expect the port hardware to include matching of the new P_Key table entry for all packets going through the port, and packets with packet P_Key value matching the new value in the updated P_Key table entry can be accepted (i.e., passed through the port).

In accordance with an embodiment, when a port in a subnet is no longer supposed to be a member of a partition, the SM can clear (write zero to) the relevant P_Key table entry. Once the P_Key value has been successfully cleared (confirmed by the SMA to the SM), the SM can expect the port hardware to fail P_Key matching for all packets going through the port with a packet P_Key value corresponding to the one that was just cleared from the port P_Key table, and then drop the packet.

In accordance with an embodiment, the SM can replace a valid P_Key table entry with a new value without clearing the existing value first. The expected effect in this case is the same as if the entry contents had first been cleared and then subsequently updated with the new value.

As already described, the embodiment depicted in FIG. 11 can scale well within the confines of a subnet without a large number of partitions. However, once a large number of partitions are present within any given subnet, such as, for example, a subnet utilizing a virtualization of end nodes and one or more vSwitch architectures, the associative table lookup described above can lead to a large increase in overhead time and may not even be possible to implement in hardware if the relevant link speed requirements defined by the IB specification is to be fulfilled.

In accordance with an embodiment, instead of utilizing a P_Key table associated with each port in the IB fabric, exemplary methods and systems can instead utilize a bitmap to implement in hardware a representation of all possible P_Key values—16 bit (i.e., 64 k possible values). In such methods and systems, within a hardware implementation, each possible P_Key value can be represented as a single bit, where the value of the single bit (e.g., 1 or 0) can define whether the P_Key value is allowed (i.e., the packet is allowed to pass through the port performing the partition check) or not associated with the port (i.e., an IB packet can then be checked according to the partition enforcement rules based on correlating the packet P_Key with the bit map entry for both the limited and full member entry for that partition number according to the P_Key enforcement rules for the relevant port type defined by the IB specification).

FIG. 12 shows an exemplary InfiniBand fabric with bitmap for partition isolation, in accordance with an embodiment. As shown in FIG. 12, one or more end nodes 1241-1244 can be connected in a network fabric 1200. The network fabric 1200 can be based on a fat-tree topology, which includes a plurality of leaf switches 1211-1214, and multiple spine switches or root switches 1231-1234. Additionally, the network fabric 1200 can include one or more intermediate switches, such as switches 1221-1224. Also as shown in FIG. 12, each of the end nodes 1241-1244 can be a multi-homed node.

In accordance with an embodiment, each of the nodes 1241-1244 can belong to one or more of a number of partitions, where each partition is associated with a P_Key value. As described above, the P_Key value can be included in each packet sent within the fabric, and can allow for varying degrees of partition enforcement within the subnet. Each of the P_Key values can be referenced in a number of bitmaps, such as bitmaps 1201-1208, where each bitmap is associated with, for example, a port of a switch or another member of the fabric, such as a HCA port belonging (associated with) to a host node. Each bitmap 1201-1208 can be set by the subnet manager.

In accordance with an embodiment, by representing the P_Keys in a bitmap instead of an associative table lookup, this can allow for greater flexibility and decreased overhead time for partition isolation and packet routing in the fabric. Any node can be a member of any partition. This can allow any switch port to only allow P_Keys that the SM has configured to be allowed through that switch port (otherwise the packets can be dropped). By utilizing a bit-map based P_Key table, the methods and systems can allow just a few partitions or several hundreds. Such methods and systems can ensure that only those partitions that are supposed to pass through a switch are allowed. Such methods and systems can allow for greater partition isolation, even with a larger number of partitions available.

In accordance with an embodiment, by using a bitmap scheme, instead of having an associative lookup of P_Key values, the hardware can take the P_Key value from the packet header, and instead of sending value into associative lookup mechanism, it instead takes the P_Key value and indexes it into a bit array (e.g., of 64K bits). An IB packet can then be checked according to the partition enforcement rules based on correlating the packet P_Key with the bit map entry for both the limited and full member entry for that partition number according to the P_Key enforcement rules for the relevant port type defined by the IB specification. This can, for example, lead to increased scaling (i.e., allowing a greater number of partition P_Keys without loss of performance).

In accordance with an embodiment, the bitmap scheme described above can, in addition to enforcing partition isolation at end nodes, additionally support partition enforcement at intermediate switches, such as at a first leaf switch for the ports connected directed to end nodes, any switch between the first leaf switch and a root switch, and at a last leaf switch. Switch to switch links are used by many different nodes, depending the routing of the fabric. In traditional systems, partition enforcement was primarily used on end nodes, and it may have been enforced at a last leaf switch for the ports connected directly to end nodes, but not switches at levels higher than leaf switches (i.e., partition enforcement was not used on links between switches). However, with the speed and efficiency gained by using a partition bitmap associated with allowed and not allowed P_Keys, partition enforcement can take place at these intermediate links. By ensuring that each switch port only allows partitions that are allowed to be sent across that port, then such a packet that encounters a port it is not allowed to pass at an intermediate link could be dropped much sooner (instead of at the end node or at the leaf switch), which allows for less performance waste in terms of link bandwidth utilization for packets that will eventually be dropped.

In accordance with an embodiment, the SM can determine and set, at the bitmaps, which traffic is allowed to be routed where in the complete fabric, depending on partition. The SM can then set up partition enforcement using the bitmap. The SM can receive policy configuration about which end nodes are members of what partition. Based on this policy information, the SM can set up partition enforcement on the end nodes (via bitmap). The SM can also configure switch to switch connectivity. Having done this, the SM can then restrict, using the bitmap, traffic flow in the fabric. SM sets values per partition in the bitmap to 1 or 0, pass or drop (i.e., allowed or not allowed). This ensures that non-allowed traffic can be dropped early on in the traffic's routing, instead of at the destination node or the last leaf switch before the destination node.

In accordance with an embodiment, each of the bitmaps can be a bit array comprising a 64K bit array for P_Key enforcement for each port. Such a bitmap can be associated with any kind of IB port: A switch external port, a switch management port (i.e., switch port 0), a TCA port (e.g. for an IB-Ethernet bridge/gateway node implementation), a HCA port as well as a router port. The IB packet can then be checked according to the partition enforcement rules based on correlating the packet P_Key with the bit map entry for both the limited and full member entry for that partition number according to the P_Key enforcement rules for the relevant port type defined by the IB specification.

In accordance with an embodiment, a single partition number can be associated with two bit array indexes—one that represents limited membership and one that represents full membership. Hence, depending on whether the port is supposed to only represent full membership or both full and limited membership, only the full member index or both the full and limited member index has to be set up to allow the corresponding membership traffic. However, due to fact that a limited partition member is not allowed to communicate with another limited member whereas a full member is allowed to communicate with both full members and limited members, the lookup implementation must take this into account so that an end-node that is initiating a packet is only allowed to send limited member packets when it is only a limited member of the partition, but that it correspondingly will only be allowed to receive full member packets.

FIG. 13 is a flowchart for a method for supporting scalable bitmap based P_Key table in a high performance computing environment, in accordance with an embodiment.

At step 1310, a packet can originate from a source (e.g., a source node or a source virtual machine) and be addressed to a destination (e.g., a destination node or a destination virtual machine). The packet can contain a header, which can include, among other information, a P_Key value corresponding to partition information, such as a common partition between the source and the destination.

At step 1320, the packet can begin traversing a fabric, such as an InfiniBand fabric, along a calculated route. The route can be calculated, for example, by a subnet manager.

At step 1330, the packet can arrive at an addressed port of a switch along the routed path within the fabric.

At step 1340, the switch at which the addressed port is located can check the packet P_Key against the contents of the bitmap (i.e., the IB packet can be checked according to the partition enforcement rules based on correlating the packet P_Key with the bitmap entry for both the limited and full member entry for that partition number according to the P_Key enforcement rules for the relevant port type defined by the IB specification).

At step 1350, if a result of the checking is “allowed”, this allows the packet to proceed along the routed path to the destination (DLID).

At step 1360, if a result of the checking is a “disallowed”, the switch can drop the packet at the addressed port and not allow the packet to proceed along the routed path.

It should be understood that although the embodiment shown in FIG. 13 and described above discloses the checking of the packet P_Key at only one switch within the fabric, each switch and node along the routed path can perform checking of the P_Key using associated bitmaps at each addressed port to determine if the packet is allowed or disallowed

Configurable Legacy P_Key Table Abstraction Using a Bitmap Based HW Implementation

In accordance with an embodiment, the above bitmap based implementation suffers in that it cannot be used directly by a legacy subnet manager implementation. This is because currently defined management entities, such as a subnet manager defined within the InfiniBand specification (i.e., InfiniBand® Trade Association Architecture Specification, Volume 1, Version 1.3, released March, 2015), are not defined to interact with a bitmap based P_Key implementation they are instead defined to interact with a legacy P_Key table based scheme defined by the IB specification.

In accordance with an embodiment, a mapping table in DRAM can be achieved through the use of a software based SMA that implements the mapping table. With this mapping table, it is possible to provide a legacy compliant view of a bit map based P_Key table. Such a legacy compliant view can be called a virtual P_Key table, or a configurable legacy P_Key table abstraction.

In accordance with an embodiment, the size of the virtual P_Key table is limited by the amount of DRAM that can be allocated for the purpose. In certain embodiments, the amount of DRAM that is accessible is contained within the switch, or other device (such as an end node) associated with the virtual P_Key table. In certain embodiments, an external source of DRAM can be utilized in order to make a larger virtual P_Key table accessible by the management entity.

In accordance with an embodiment, each virtual P_Key table can have a configuration parameter (or header file constant) defined size, and can be implemented by a corresponding memory data structure (e.g., embedded processor subsystem memory data structure (EPS)) associated with the relevant SMA attributes instance.

In accordance with an embodiment, whenever the management entity (e.g., subnet manager) stores a P_Key value in a (virtual) P_Key table entry that is currently cleared (contains the value zero), the SMA implementation can invoke the HW access layer to set the HW bit array indexed by the P_Key value to one, and can then update the virtual P_Key table entry (e.g., the EPS memory data structure) so that the P_Key table entry number specified by the SM will contain the specified P_Key value.

In accordance with an embodiment, whenever the SM clears a P_Key value from an entry in the virtual P_Key table, the SMA implementation can use the old P_Key value from the memory data structure and then clear the corresponding HW bit array index via the HW access interface before the virtual P_Key table entry (i.e. the EPS memory data structure) is also cleared.

In accordance with an embodiment, whenever the SM writes a new P_Key value to a (virtual) P_Key table entry that is not currently cleared, the SMA implementation can first use the old P_Key value from the EPS memory data structure and then clear the corresponding HW bit array index via the HW access interface. After the old value has been cleared, the SMA implementation can set the bit array entry corresponding to the newly added P_Key value and then update the memory data structure so that the specified P_Key table entry will now contain the specified P_Key value.

FIG. 14 shows an exemplary fabric with bitmap for partition isolation and a P_Key abstraction for legacy management entity, in accordance with an embodiment. In the embodiment shown in the figure, a switch 1400 can comprise a number of ports 1420, and each of these ports can be associated with a bitmap based P_Key table 1410 for P_Key enforcement, as described above. The switch 1400 can additionally comprise a memory (e.g., DRAM) 1430.

In accordance with an embodiment, a subnet manager 1440 (e.g., a legacy subnet manager) can be incapable of querying/setting the bitmap based P_Key table 1410. In such a situation, a P_Key table abstraction 1450 (i.e., a “virtual P_Key table”) can be provided within the memory 1430 of the switch. Then, the subnet manager, can query and interact with the virtual P_Key table in the same way that the subnet manager would interact with a legacy P_Key table based on associative memory/lookup. More specifically, the SM 1440 can interface with a SMA 1441 associated with the switch 1400. This interface can utilize IB specification defined SMA attributes and methods for P_Key management, and thus the SM has no knowledge about the underlying implementation.

In accordance with an embodiment, because each P_Key contained in the virtual P_Key table comprises 16 bits, and because of the number of potential P_Key values to be contained in the virtual P_Key table (i.e., up to 64K P_Keys), the size of a virtual P_Key table can be limited by the amount of memory 1430 contained in the switch and/or allocated by the switch to the virtual P_Key table. For example, in order to represent 64K P_Keys for each port in a 36 port switch the require memory size can be greater than 4 megabytes.

FIG. 15 shows an exemplary fabric with bitmap for partition isolation and a P_Key abstraction for legacy management entity, in accordance with an embodiment. In the embodiment shown in the figure, a switch 1400 can comprise a number of ports 1420, and each of these ports can be associated with a bitmap based P_Key table 1410 for P_Key enforcement, as described above. An external memory 1530 can be accessed by the switch 1400.

In accordance with an embodiment, a subnet manager 1440 (e.g., a legacy subnet manager) can be incapable of querying/setting the bitmap based P_Key table 1410. In such a situation, a P_Key table abstraction 1450 (i.e., a “virtual P_Key table”) can be provided within the external memory 1530. Then, the subnet manager, can query and intact with the virtual P_Key table in the same way that the subnet manager would interact with a legacy P_Key table based on associative memory/lookup. More specifically, the SM 1440 can interface with a SMA 1441 associated with the switch 1400 to perform such a query. This interface can utilize IB specification defined SMA attributes and methods for P_Key management, and thus the SM has no knowledge about the underlying implementation.

In accordance with an embodiment, because each P_Key contained in the virtual P_Key table comprises 16 bits, and because of the number of potential P_Key values to be contained in the virtual P_Key table (i.e., up to 64K P_Keys), the size of a virtual P_Key table can be limited by the amount of external memory 1530. Unlike the situation described above, the external memory can often be much larger than the amount of memory contained at the switch itself. In such situations, the potential size of the virtual P_Key table is much larger than that described above with respect to FIG. 14. In such a case, for example, it would be possible to represent 64K P_Keys for each switch port.

FIG. 16 is a flowchart for a method for supporting legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment, in accordance with an embodiment. The method can Provide, at one or more computers, including one or more microprocessors, at least one subnet, the at least one subnet comprising one or more switches, the one or more switches comprising at least a leaf switch, wherein each of the one or more switches comprise a plurality of switch ports, a plurality of host channel adapters, each host channel adapter comprising at least one host channel adapter port, and a plurality of end nodes, wherein each of the plurality of end nodes are associated with at least one host channel adapter of the plurality of host channel adapters.

At step 1620, the method can associate each of the plurality of end nodes with at least one of a plurality of partitions, wherein each of the plurality of partitions are associated with a P_Key value.

At step 1630, the method can associate each of the switch ports of the one or more switches with a bitmap based P_Key table of a plurality of bitmap based P_Key tables.

At step 1640, the method can associate each of the host channel adapter ports with a bitmap based P_Key table of the plurality of bitmap based P_Key tables.

At step 1650, the method can associate each of the plurality of bitmap based P_Key tables with a virtual P_Key table.

Many features of the present invention can be performed in, using, or with the assistance of hardware, software, firmware, or combinations thereof. Consequently, features of the present invention may be implemented using a processing system (e.g., including one or more processors).

Features of the present invention can be implemented in, using, or with the assistance of a computer program product which is a storage medium (media) or computer readable medium (media) having instructions stored thereon/in which can be used to program a processing system to perform any of the features presented herein. The storage medium can include, but is not limited to, any type of disk including floppy disks, optical discs, DVD, CD-ROMs, microdrive, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of media or device suitable for storing instructions and/or data.

Stored on any one of the machine readable medium (media), features of the present invention can be incorporated in software and/or firmware for controlling the hardware of a processing system, and for enabling a processing system to interact with other mechanism utilizing the results of the present invention. Such software or firmware may include, but is not limited to, application code, device drivers, operating systems and execution environments/containers.

Features of the invention may also be implemented in hardware using, for example, hardware components such as application specific integrated circuits (ASICs). Implementation of the hardware state machine so as to perform the functions described herein will be apparent to persons skilled in the relevant art.

Additionally, the present invention may be conveniently implemented using one or more conventional general purpose or specialized digital computer, computing device, machine, or microprocessor, including one or more processors, memory and/or computer readable storage media programmed according to the teachings of the present disclosure. Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will be apparent to those skilled in the software art.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention.

The present invention has been described above with the aid of functional building blocks illustrating the performance of specified functions and relationships thereof. The boundaries of these functional building blocks have often been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Any such alternate boundaries are thus within the scope and spirit of the invention.

The foregoing description of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments. Many modifications and variations will be apparent to the practitioner skilled in the art. The modifications and variations include any relevant combination of the disclosed features. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents. 

What is claimed is:
 1. A system for supporting legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment, comprising: one or more microprocessors; at least one subnet, the at least one subnet comprising one or more switches, the one or more switches comprising at least a leaf switch, wherein each of the one or more switches comprise a plurality of switch ports, a plurality of host channel adapters, each host channel adapter comprising at least one host channel adapter port, and a plurality of end nodes, wherein each of the plurality of end nodes are associated with at least one host channel adapter of the plurality of host channel adapters; wherein each of the plurality of end nodes are associated with at least one of a plurality of partitions; wherein each of the plurality of partitions are associated with a P_Key value; wherein one or more of the switch ports are associated with a bitmap based P_Key table of a plurality of bitmap based P_Key tables; wherein one or more of the host channel adapter ports are associated with a bitmap based P_Key table of the plurality of bitmap based P_Key tables; and wherein each of the plurality of bitmap based P_Key tables are associated with a virtual P_Key table.
 2. The system of claim 1, further comprising: a subnet manager, the subnet manager operating via one of the plurality of end nodes; wherein the subnet manager determines allowed and disallowed traffic through the plurality of ports on each of the one or more switches.
 3. The system of claim 2, wherein the subnet manager configures, via an associated virtual P_Key table, each of the bitmap based P_Key tables based upon the determination of allowed and disallowed traffic through each of the plurality of ports on each of the one or more switches.
 4. The system of claim 3, wherein the each of the virtual P_Key tables are hosted on memory at the respective switches and host channel adapters.
 5. The system of claim 4, wherein each of the virtual P_Key tables are limited in size based upon an amount of memory at the respective switches and host channel adapters.
 6. The system of claim 3, wherein each of the virtual P_Key tables are hosted on memory external from the respective switches and host channel adapters.
 7. The system of claim 1, wherein the systems comprises two or more subnets, each of the two or more subnets being interconnected by at least one router port in each of the two or more subnets.
 8. A method for supporting legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment, comprising: providing, at one or more computers, including one or more microprocessors, at least one subnet, the at least one subnet comprising one or more switches, the one or more switches comprising at least a leaf switch, wherein each of the one or more switches comprise a plurality of switch ports, a plurality of host channel adapters, each host channel adapter comprising at least one host channel adapter port, a plurality of end nodes, wherein each of the end nodes are associated with at least one host channel adapter of the plurality of host channel adapters, and associating each of the plurality of end nodes with at least one of a plurality of partitions, wherein each of the plurality of partitions are associated with a P_Key value; associating each of the one or more switch ports with a bitmap based P_Key table of a plurality of bitmap based P_Key tables; associating each of the host channel adapter ports with a bitmap based P_Key table of the plurality of bitmap based P_Key tables; and associating each of the plurality of bitmap based P_Key tables with a virtual P_Key table.
 9. The method of claim 8, further comprising: further providing, at the one or more computers, including the one or more microprocessors, a subnet manager, the subnet manager operating via one of the plurality of end nodes; and determining, by the subnet manager, allowed and disallowed traffic through the plurality of ports on each of the one or more switches.
 10. The method of claim 9 further comprising, configuring, by the subnet manager via an associated virtual P_Key table, each of the bitmap based P_Key tables based upon the determination of allowed and disallowed traffic through each of the plurality of ports on each of the one or more switches.
 11. The method of claim 10, wherein the each of the virtual P_Key tables are hosted on memory at the respective switches and host channel adapters.
 12. The method of claim 11, wherein each of the virtual P_Key tables are limited in size based upon an amount of memory at the respective switches and host channel adapters.
 13. The method of claim 10, wherein each of the virtual P_Key tables are hosted on memory external from the respective switches and host channel adapters.
 14. The method of claim 8, wherein the one or more subnets comprise two or more subnets, each of the two or more subnets being interconnected by at least one router in each of the two or more subnets.
 15. A non-transitory computer readable storage medium, including instructions stored thereon for supporting legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment, which when read and executed by one or more computers cause the one or more computers to perform steps comprising: providing, at one or more computers, including one or more microprocessors, at least one subnet, the at least one subnet comprising one or more switches, the one or more switches comprising at least a leaf switch, wherein each of the one or more switches comprise a plurality of switch ports, a plurality of host channel adapters, each host channel adapter comprising at least one host channel adapter port, a plurality of end nodes, wherein each of the end nodes are associated with at least one host channel adapter of the plurality of host channel adapters, and associating each of the plurality of end nodes with at least one of a plurality of partitions, wherein each of the plurality of partitions are associated with a P_Key value; associating each of the one or more switch ports with a bitmap based P_Key table of a plurality of bitmap based P_Key tables; associating each of the host channel adapter ports with a bitmap based P_Key table of the plurality of bitmap based P_Key tables; and associating each of the plurality of bitmap based P_Key tables with a virtual P_Key table.
 16. The non-transitory computer readable storage medium of claim 15, the steps further comprising: further providing, at the one or more computers, including the one or more microprocessors, a subnet manager, the subnet manager operating via one of the plurality of end nodes; and determining, by the subnet manager, allowed and disallowed traffic through the plurality of ports on each of the one or more switches.
 17. The non-transitory computer readable storage medium of claim 16, the steps further comprising, configuring, by the subnet manager via an associated virtual P_Key table, each of the bitmap based P_Key tables based upon the determination of allowed and disallowed traffic through each of the plurality of ports on each of the one or more switches.
 18. The non-transitory computer readable storage medium of claim 17, wherein the each of the virtual P_Key tables are hosted on memory at the respective switches and host channel adapters.
 19. The non-transitory computer readable storage medium of claim 18, wherein each of the virtual P_Key tables are limited in size based upon an amount of memory at the respective switches and host channel adapters.
 20. The non-transitory computer readable storage medium of claim 17, wherein each of the virtual P_Key tables are hosted on memory external from the respective switches and host channel adapters. 